Also, the yield isn't great. 10 devices failed short out of 216 produced. That's not going to get you something a whole lot better than a few gates or memory cells or a few opamps.
The 3D printing world has exploded. I sort of wonder if homemade ICs might do the same if some additive process can be made friendly and robust enough. Making my own low-performance chips for hobbydollars would be awesome.
Well, of course, it would be hard. But a 1cm² 22nm die could largely fit (186cm²) into a sheet of paper with a 300nm feature length.
And most modern designs are more concerned with gate length, so 22nm->7nm doesn't exactly translate into the expected area gains for the whole chip.
One of the downsides of bigger chips is that we're more sensitive to propagation delays and capacitances. On the flip side, capacitors are easier to make. That would likely lead to new architectures: fully asynchronous, maximizing throughput over single thread performance.
That'd be quite interesting for neuromorphic architectures, and would likely displace FPGAs in a lot of situations if printers (or circuits) were affordable.
Now, imagine 3D integration: that would be… a book!
More seriously, having bigger chips to work with means that the contacts can be bigger, thus easier to align. We could also start blurring lines between PCB and IC design, bringing discrete components inside ICs.
I admit I don't know yet what a practical size would be, but the last talk I saw on the topic used organic semiconductors, and the channel length was on the order of millimeters. Despite this, it already had quite a lot of potential.
Surely determining which trace is connected to which would be hard at intersections, but:
- You can hypothetically print it yourself, scanning each layer separately
- I wonder if some design patterns couldn't be used to prove the circuit wouldn't work if a crossing point was shorted or cut
- you could have additionnal, easier-to-check verification circuits
- if ordering big circuits, it might be possible to order them whole, as well as layer-by-layer. One could verify each layer, measure it, compute the inertia matrix of the whole and verify it matches.
If the feature size is big, though, I'd be wary of discrete components that could have been planted there.
If I could print a TMS-1000 or a 6502 on something the size of a postage stamp, using equipment I could reasonably keep in a home workshop, it would be enormously useful. Think embedded, not replacing your desktop.
I think if anyone will replicate this, a 6502 will be one of the first projects. After all, the feature size is the main thing that prevents the discrete component replicas from being drop-in replacements: https://monster6502.com/
Inkjet ink and "hobbydollars" don't mix very well. I'm going to guess that this process is going to end up being a lot more expensive than getting the devices via your average silicon fab.
This is not inkjet ink. Calling this process inkjet is pretty misleading IMO, because other than multi-nozzle piezo deposition of defined amounts of liquid, this printer doesn't have much in common with your consumer inkjet. I mean, it has a permanent "ink" tank resilient against most chemicals and a z axis for multi-layer deposition.
The inks involved are nano-particle inks (commercially available) and a customer 20% CNT ink, for multiple layers of unaligned CNT. That's really the missing info here - their secret. What is this mistery solution which can dissolve CNT, anneal away, and overcome the hydroscopicity of CNT. The latter is the key to this whole process.
If we had more info on the solution, I think we would have seen some hobbyists with deep pockets replicate this by now. Keep in mind there already are hobbyists with homebrew silicon IC fabs.
To put into perspective: IIRC, one should set aside $5M for a mask set if planning to use advanced processes. Our multi-project wafers, from 130 to 22 nm, cost us ~€10k per mm².
You have to multiply by the number of different circuits.
Inkjet (or more generally fabless) allow you to get closer to individual unit costs right away for prototyping.
I'm not sure everyone could buy one such printer (I haven't looked at the prices), but a billion-dollars fab sure isn't affordable.
As an aside, IPs for integrated circuits are so expensive rightly because they generally have to be prototyped trough before being sold. I guess it's one of a few domains where engineering costs are quite low compared to fabrication costs.
This development looks very important: 10^6 on/off conductivity ratio, 18 GHz bandwidth.
The method is brilliantly simple: source ink hydrophobic, drain ink hydrophilic, gate width is the gap they create when the incompatible solutions start out in contact.
Silver nanoparticle inks are being tested for various health effects. One recent study found:
> Silver nanoparticles cause more damage to testicular cells than titanium dioxide nanoparticles, according to a recent study by the Norwegian Institute of Public Health. However, the use of both types may affect testicular cells with possible consequences for fertility.
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Also, the yield isn't great. 10 devices failed short out of 216 produced. That's not going to get you something a whole lot better than a few gates or memory cells or a few opamps.
The 3D printing world has exploded. I sort of wonder if homemade ICs might do the same if some additive process can be made friendly and robust enough. Making my own low-performance chips for hobbydollars would be awesome.